5G-LENA nr-v3.3-49-g235218b1
The 5G/NR module for the ns-3 simulator
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nr-phy-mac-common.h
1// Copyright (c) 2011 Centre Tecnologic de Telecomunicacions de Catalunya (CTTC)
2// Copyright (c) 2015, NYU WIRELESS, Tandon School of Engineering, New York University
3// Copyright (c) 2019 Centre Tecnologic de Telecomunicacions de Catalunya (CTTC)
4//
5// SPDX-License-Identifier: GPL-2.0-only
6
7#ifndef SRC_NR_MODEL_NR_PHY_MAC_COMMON_H
8#define SRC_NR_MODEL_NR_PHY_MAC_COMMON_H
9
10#include "nr-error-model.h"
11#include "sfnsf.h"
12
13#include <ns3/log.h>
14#include <ns3/matrix-array.h>
15#include <ns3/object.h>
16#include <ns3/string.h>
17
18#include <deque>
19#include <list>
20#include <map>
21#include <memory>
22#include <unordered_map>
23#include <vector>
24
25namespace ns3
26{
27
29{
30 template <class First, class Second>
31 First& operator()(std::pair<First, Second>& p)
32 {
33 return p.first;
34 }
35
36 template <class First, class Second>
37 First& operator()(typename std::map<First, Second>::iterator& p)
38 {
39 return p.first;
40 }
41
42 template <class First, class Second>
43 const First& operator()(const std::pair<First, Second>& p)
44 {
45 return p.first;
46 }
47
48 template <class First, class Second>
49 const First& operator()(const typename std::map<First, Second>::iterator& p)
50 {
51 return p.first;
52 }
53};
54
56{
57 template <class First, class Second>
58 Second& operator()(std::pair<First, Second>& p)
59 {
60 return p.second;
61 }
62
63 template <class First, class Second>
64 Second& operator()(typename std::map<First, Second>::iterator& p)
65 {
66 return p.second;
67 }
68
69 template <class First, class Second>
70 Second& operator()(typename std::unordered_map<First, Second>::iterator& p)
71 {
72 return p.second;
73 }
74
75 template <class First, class Second>
76 const Second& operator()(const std::pair<First, Second>& p)
77 {
78 return p.second;
79 }
80
81 template <class First, class Second>
82 const Second& operator()(const typename std::map<First, Second>::iterator& p)
83 {
84 return p.second;
85 }
86
87 template <class First, class Second>
88 const Second& operator()(const typename std::unordered_map<First, Second>::iterator& p)
89 {
90 return p.second;
91 }
92};
93
97enum CsiFeedbackFlag : uint8_t
98{
99 CQI_PDSCH_MIMO = 0x01,
100 CQI_CSI_RS = 0x02,
101 CQI_CSI_IM = 0x04,
102 CQI_PDSCH_SISO = 0x08
103};
104
110{
115 {
116 DL = 0,
117 UL = 1
118 };
119
124 {
125 SRS = 0,
126 DATA = 1,
127 CTRL = 2,
128 MSG3 = 3,
129 };
130
137 DciInfoElementTdma(uint8_t symStart,
138 uint8_t numSym,
139 DciFormat format,
140 VarTtiType type,
141 const std::vector<uint8_t>& rbgBitmask)
142 : m_format(format),
143 m_symStart(symStart),
144 m_numSym(numSym),
145 m_type(type),
146 m_rbgBitmask(rbgBitmask)
147 {
148 }
149
165 DciInfoElementTdma(uint16_t rnti,
166 DciFormat format,
167 uint8_t symStart,
168 uint8_t numSym,
169 uint8_t mcs,
170 uint8_t rank,
171 Ptr<const ComplexMatrixArray> precMats,
172 uint32_t tbs,
173 uint8_t ndi,
174 uint8_t rv,
175 VarTtiType type,
176 uint8_t bwpIndex,
177 uint8_t tpc)
178 : m_rnti(rnti),
179 m_format(format),
180 m_symStart(symStart),
181 m_numSym(numSym),
182 m_mcs(mcs),
183 m_rank(rank),
184 m_precMats(precMats),
185 m_tbSize(tbs),
186 m_ndi(ndi),
187 m_rv(rv),
188 m_type(type),
189 m_bwpIndex(bwpIndex),
190 m_tpc(tpc)
191 {
192 }
193
202 DciInfoElementTdma(uint8_t symStart,
203 uint8_t numSym,
204 uint8_t ndi,
205 uint8_t rv,
206 const DciInfoElementTdma& o)
207 : m_rnti(o.m_rnti),
209 m_symStart(symStart),
210 m_numSym(numSym),
211 m_mcs(o.m_mcs),
212 m_rank(o.m_rank),
213 m_precMats(o.m_precMats),
215 m_ndi(ndi),
216 m_rv(rv),
217 m_type(o.m_type),
221 m_tpc(o.m_tpc)
222 {
223 }
224
225 const uint16_t m_rnti{0};
227 const uint8_t m_symStart{0};
228 const uint8_t m_numSym{0};
229 const uint8_t m_mcs{0};
230 const uint8_t m_rank{1};
231 Ptr<const ComplexMatrixArray> m_precMats{nullptr};
232 const uint32_t m_tbSize{0};
233 const uint8_t m_ndi{0};
234 const uint8_t m_rv{0};
236 const uint8_t m_bwpIndex{0};
237 uint8_t m_harqProcess{0};
238 std::vector<uint8_t> m_rbgBitmask{};
239 const uint8_t m_tpc{0};
240};
241
247{
248 RlcPduInfo() = default;
249 RlcPduInfo(const RlcPduInfo& o) = default;
250 ~RlcPduInfo() = default;
251
252 RlcPduInfo(uint8_t lcid, uint32_t size)
253 : m_lcid(lcid),
254 m_size(size)
255 {
256 }
257
258 uint8_t m_lcid{0};
259 uint32_t m_size{0};
260};
261
263{
264 VarTtiAllocInfo(const VarTtiAllocInfo& o) = default;
265
266 VarTtiAllocInfo(const std::shared_ptr<DciInfoElementTdma>& dci)
267 : m_dci(dci)
268 {
269 }
270
271 bool m_isOmni{false};
272 std::shared_ptr<DciInfoElementTdma> m_dci;
273 std::vector<RlcPduInfo> m_rlcPduInfo;
274
275 bool operator<(const VarTtiAllocInfo& o) const
276 {
277 NS_ASSERT(m_dci != nullptr);
278 return (m_dci->m_symStart < o.m_dci->m_symStart);
279 }
280};
281
283{
284 std::shared_ptr<DciInfoElementTdma>
286 uint8_t raPreambleId{255};
287 uint32_t k2Delay{100};
289};
290
296{
298 : m_sfnSf(sfn)
299 {
300 }
301
306 {
307 NONE = 0,
308 DL = 1,
309 UL = 2,
310 BOTH = 3
311 };
312
319 void Merge(const SlotAllocInfo& other);
320
325 bool ContainsDataAllocation() const;
326
331 bool ContainsUlMsg3Allocation() const;
332
336 bool ContainsDlCtrlAllocation() const;
337
341 bool ContainsUlCtrlAllocation() const;
342
344 uint32_t m_numSymAlloc{0};
345 std::deque<VarTtiAllocInfo> m_varTtiAllocInfo;
347 std::vector<NrBuildRarListElement_s> m_buildRarList;
355 bool operator<(const SlotAllocInfo& rhs) const;
356};
357
363{
364 uint16_t m_rnti{0};
365 // TODO: Rename to m_rank (m_ri is set directly to the rank).
366 uint8_t m_ri{0};
367
368 // TODO: use NrMacSchedulerUeInfo::CqiInfo
369 enum DlCqiType
370 {
371 WB,
372 SB
373 } m_cqiType{WB};
374
375 uint8_t m_wbCqi{0};
376 size_t m_wbPmi{0};
377
378 std::vector<uint8_t> m_sbCqis;
379 std::vector<size_t> m_sbPmis;
380 uint8_t m_mcs{0};
381 Ptr<const ComplexMatrixArray> m_optPrecMat{};
382};
383
389{
390 uint8_t m_mcs{0};
391 uint8_t m_rank{0};
392 size_t m_wbPmi{0};
393 uint8_t m_wbCqi{0};
394 std::vector<uint8_t> m_sbCqis;
395 std::vector<size_t> m_sbPmis;
396 Ptr<const ComplexMatrixArray> m_optPrecMat{};
397
398 // TODO: Fix/remove empty DlSBCQIReported, then change default type to SB.
399
400 DlCqiInfo::DlCqiType m_cqiType{DlCqiInfo::WB};
401 size_t m_tbSize{};
402};
403
409{
410 // std::vector <uint16_t> m_sinr;
411 std::vector<double> m_sinr;
412
413 enum UlCqiType
414 {
415 SRS,
416 PUSCH,
417 PUCCH_1,
418 PUCCH_2,
419 PRACH
420 } m_type;
421};
422
428{
429 MacCeValue()
430 : m_phr(0),
431 m_crnti(0)
432 {
433 }
434
435 uint8_t m_phr;
436 uint8_t m_crnti;
437 std::vector<uint8_t> m_bufferStatus;
438};
439
445{
447 : m_rnti(0)
448 {
449 }
450
451 uint16_t m_rnti;
452
453 enum MacCeType
454 {
455 BSR,
456 PHR,
457 CRNTI
458 } m_macCeType;
459 struct MacCeValue m_macCeValue;
460};
461
467{
468 std::vector<struct RlcPduInfo> m_rlcPduElements;
469};
470
476{
477 uint64_t m_imsi;
478 uint32_t m_noBytes;
479 bool m_isTx; // Set to false if Rx and true if tx
480 uint32_t m_subframeno;
481};
482
488{
489 uint64_t m_cellId;
490 uint32_t m_noBytes;
491 bool m_isTx; // Set to false if Rx and true if tx
492 uint32_t m_subframeno;
493};
494
502{
503 ExpectedTb(uint8_t ndi,
504 uint32_t tbSize,
505 uint8_t mcs,
506 uint8_t rank,
507 uint16_t rnti,
508 const std::vector<int>& rbBitmap,
509 uint8_t harqProcessId,
510 uint8_t rv,
511 bool isDownlink,
512 uint8_t symStart,
513 uint8_t numSym,
514 const SfnSf& sfn)
515 : m_ndi(ndi),
516 m_tbSize(tbSize),
517 m_mcs(mcs),
518 m_rank(rank),
519 m_rnti(rnti),
520 m_rbBitmap(rbBitmap),
521 m_harqProcessId(harqProcessId),
522 m_rv(rv),
523 m_isDownlink(isDownlink),
524 m_symStart(symStart),
525 m_numSym(numSym),
526 m_sfn(sfn)
527 {
528 }
529
530 ExpectedTb() = delete;
531 ExpectedTb(const ExpectedTb& o) = default;
532
533 uint8_t m_ndi{0};
534 uint32_t m_tbSize{0};
535 uint8_t m_mcs{0};
536 uint8_t m_rank{1};
537 uint16_t m_rnti{0};
538 std::vector<int> m_rbBitmap;
539 uint8_t m_harqProcessId{0};
540 uint8_t m_rv{0};
541 bool m_isDownlink{false};
542 uint8_t m_symStart{0};
543 uint8_t m_numSym{0};
545};
546
548{
549 TransportBlockInfo(const ExpectedTb& expected)
550 : m_expected(expected)
551 {
552 }
553
554 TransportBlockInfo() = delete;
555
560 void UpdatePerceivedSinr(const SpectrumValue& perceivedSinr);
561
563 bool m_isCorrupted{false};
564 // Filled at the end of data rx/tx
565 bool m_harqFeedbackSent{false};
566 Ptr<NrErrorModelOutput> m_outputOfEM;
567 double m_sinrAvg{0.0};
568 double m_sinrMin{0.0};
569};
570
576{
578 bool errorModelEnabled,
579 uint16_t rnti,
580 uint16_t cellId,
581 uint16_t bwpId,
582 uint8_t cqi)
583 : m_cellId(cellId),
584 m_rnti(rnti),
585 m_frameNum(tbInfo.m_expected.m_sfn.GetFrame()),
586 m_subframeNum(tbInfo.m_expected.m_sfn.GetSubframe()),
587 m_slotNum(tbInfo.m_expected.m_sfn.GetSlot()),
588 m_symStart(tbInfo.m_expected.m_symStart),
589 m_numSym(tbInfo.m_expected.m_numSym),
590 m_tbSize(tbInfo.m_expected.m_tbSize),
591 m_mcs(tbInfo.m_expected.m_mcs),
592 m_rank(tbInfo.m_expected.m_rank),
593 m_rv(tbInfo.m_expected.m_rv),
594 m_sinr(tbInfo.m_sinrAvg),
595 m_sinrMin(tbInfo.m_sinrMin),
596 m_tbler(errorModelEnabled ? tbInfo.m_outputOfEM->m_tbler : 0),
597 m_corrupt(errorModelEnabled && tbInfo.m_isCorrupted),
598 m_bwpId(bwpId),
599 m_rbAssignedNum(static_cast<uint32_t>(tbInfo.m_expected.m_rbBitmap.size())),
600 m_cqi(cqi){};
601 uint64_t m_cellId{0};
602 uint16_t m_rnti{0};
603 uint32_t m_frameNum{std::numeric_limits<uint32_t>::max()};
604 uint8_t m_subframeNum{std::numeric_limits<uint8_t>::max()};
605 uint16_t m_slotNum{std::numeric_limits<uint16_t>::max()};
606 uint8_t m_symStart{std::numeric_limits<uint8_t>::max()};
607 uint8_t m_numSym{std::numeric_limits<uint8_t>::max()};
608 uint32_t m_tbSize{0};
609 uint8_t m_mcs{std::numeric_limits<uint8_t>::max()};
610 uint8_t m_rank{std::numeric_limits<uint8_t>::max()};
611 uint8_t m_rv{std::numeric_limits<uint8_t>::max()};
612 double m_sinr{-1.0};
613 double m_sinrMin{-1.0};
614 double m_tbler{-1.0};
615 bool m_corrupt{false};
616 uint16_t m_bwpId{std::numeric_limits<uint16_t>::max()};
617 uint32_t m_rbAssignedNum{std::numeric_limits<uint32_t>::max()};
618 uint8_t m_cqi{std::numeric_limits<uint8_t>::max()};
619};
620
629{
630 virtual ~HarqInfo()
631 {
632 }
633
634 uint16_t m_rnti{UINT16_MAX};
635 uint8_t m_harqProcessId{UINT8_MAX};
636 uint8_t m_bwpIndex{UINT8_MAX};
637
642 virtual bool IsReceivedOk() const = 0;
643};
644
652struct DlHarqInfo : public HarqInfo
653{
658 {
659 ACK,
660 NACK
661 } m_harqStatus{NACK};
662
663 uint8_t m_numRetx;
664
665 bool IsReceivedOk() const override
666 {
667 return m_harqStatus == ACK;
668 }
669};
670
675struct UlHarqInfo : public HarqInfo
676{
677 std::vector<uint16_t> m_ulReception;
678
679 enum ReceptionStatus
680 {
681 Ok,
682 NotOk,
683 NotValid
684 } m_receptionStatus;
685
686 uint8_t m_tpc{UINT8_MAX};
687 uint8_t m_numRetx{UINT8_MAX};
688
689 bool IsReceivedOk() const override
690 {
691 return m_receptionStatus == Ok;
692 }
693};
694
695namespace nr
696{
697
701struct VendorSpecificValue : public SimpleRefCount<VendorSpecificValue>
702{
703 virtual ~VendorSpecificValue(){};
704};
705
711{
712 uint32_t m_type{UINT32_MAX};
713 uint32_t m_length{UINT32_MAX};
714 Ptr<VendorSpecificValue> m_value;
715};
716
722{
723 uint8_t m_logicalChannelIdentity{UINT8_MAX};
724 uint8_t m_logicalChannelGroup{UINT8_MAX};
725
728 {
729 DIR_UL,
730 DIR_DL,
731 DIR_BOTH,
733 } m_direction{NotValid};
734
737 {
738 QBT_NON_GBR,
739 QBT_GBR,
740 QBT_DGBR,
742 } m_qosBearerType{NotValid_QosBearerType};
743
744 uint8_t m_qci{UINT8_MAX};
745 uint64_t m_eRabMaximulBitrateUl{UINT64_MAX};
746 uint64_t m_eRabMaximulBitrateDl{UINT64_MAX};
747 uint64_t m_eRabGuaranteedBitrateUl{UINT64_MAX};
748 uint64_t m_eRabGuaranteedBitrateDl{UINT64_MAX};
749};
750
756{
757 uint16_t m_rnti{UINT16_MAX};
758 uint16_t m_estimatedSize{UINT16_MAX};
759};
760
765{
766 uint8_t m_phr{UINT8_MAX};
767 uint8_t m_crnti{UINT8_MAX};
768 std::vector<uint8_t> m_bufferStatus;
769};
770
775{
776 uint16_t m_rnti{UINT16_MAX};
777
780 {
781 BSR,
782 PHR,
783 CRNTI,
785 } m_macCeType{NotValid};
787};
788
789} // namespace nr
790
791std::ostream& operator<<(std::ostream& os, const DciInfoElementTdma& item);
792std::ostream& operator<<(std::ostream& os, const DciInfoElementTdma::DciFormat& item);
793std::ostream& operator<<(std::ostream& os, const DlHarqInfo& item);
794std::ostream& operator<<(std::ostream& os, const UlHarqInfo& item);
795std::ostream& operator<<(std::ostream& os, const SfnSf& item);
796std::ostream& operator<<(std::ostream& os, const SlotAllocInfo& item);
797std::ostream& operator<<(std::ostream& os, const SlotAllocInfo::AllocationType& item);
798} // namespace ns3
799
802{
803 uint16_t m_frameNum{UINT16_MAX};
804 uint8_t m_subframeNum{UINT8_MAX};
805 uint16_t m_slotNum{UINT16_MAX};
806 uint8_t m_symStart{UINT8_MAX};
807 uint8_t m_numSym{UINT8_MAX};
808 uint16_t m_rnti{UINT16_MAX};
809 uint8_t m_mcs{UINT8_MAX};
810 uint32_t m_tbSize{UINT32_MAX};
811 uint8_t m_bwpId{UINT8_MAX};
812 uint8_t m_ndi{UINT8_MAX};
813 uint8_t m_rv{UINT8_MAX};
814 uint8_t m_harqId{UINT8_MAX};
815};
816
817#endif /* SRC_NR_MODEL_NR_PHY_MAC_COMMON_H_ */
The SfnSf class.
Definition sfnsf.h:32
uint8_t GetSubframe() const
GetSubframe.
Definition sfnsf.cc:158
uint8_t GetSlot() const
GetSlot.
Definition sfnsf.cc:164
uint32_t GetFrame() const
GetFrame.
Definition sfnsf.cc:152
static std::ostream & operator<<(std::ostream &os, const TrafficTypeConf &item)
operator << for TrafficTypeConf
NrSchedulingCallbackInfo structure.
uint8_t m_ndi
New data indicator.
uint8_t m_symStart
starting symbol index
uint8_t m_subframeNum
subframe number
uint16_t m_frameNum
frame number
uint8_t m_bwpId
Bandwidth Part ID.
uint16_t m_slotNum
slot number
uint8_t m_numSym
number of symbols
Scheduling information. Despite the name, it is not TDMA.
const uint8_t m_tpc
Tx power control command.
const uint32_t m_tbSize
TB size.
DciInfoElementTdma(uint16_t rnti, DciFormat format, uint8_t symStart, uint8_t numSym, uint8_t mcs, uint8_t rank, Ptr< const ComplexMatrixArray > precMats, uint32_t tbs, uint8_t ndi, uint8_t rv, VarTtiType type, uint8_t bwpIndex, uint8_t tpc)
Construct to build brand new DCI. Please remember to update manually the HARQ process ID and the RBG ...
const DciFormat m_format
DCI format.
const uint8_t m_rank
the rank number (the number of MIMO layers)
const uint16_t m_rnti
RNTI of the UE.
const uint8_t m_bwpIndex
BWP Index to identify to which BWP this DCI applies to.
uint8_t m_harqProcess
HARQ process id.
DciInfoElementTdma(uint8_t symStart, uint8_t numSym, uint8_t ndi, uint8_t rv, const DciInfoElementTdma &o)
Copy constructor except for some values that have to be overwritten.
VarTtiType
The VarTtiType enum.
@ CTRL
Used for DL/UL CTRL.
@ DATA
Used for DL/UL DATA.
@ SRS
Used for SRS (it would be like DCI format 2_3)
std::vector< uint8_t > m_rbgBitmask
RBG mask: 0 if the RBG is not used, 1 otherwise.
DciInfoElementTdma(uint8_t symStart, uint8_t numSym, DciFormat format, VarTtiType type, const std::vector< uint8_t > &rbgBitmask)
Constructor used in NrUePhy to build local DCI for DL and UL control.
const VarTtiType m_type
Var TTI type.
const uint8_t m_symStart
starting symbol index for flexible TTI scheme
const uint8_t m_numSym
number of symbols for flexible TTI scheme
const uint8_t m_rv
Redundancy Version.
const uint8_t m_ndi
New Data Indicator.
DciFormat
Format of the DCI.
The DlCqiInfo struct.
Ptr< const ComplexMatrixArray > m_optPrecMat
Precoding matrix for each RB.
std::vector< size_t > m_sbPmis
Subband PMI values (i2, indices of W2 matrices)
uint8_t m_mcs
MCS (can be derived from CQI feedback)
size_t m_wbPmi
Wideband precoding matrix index.
uint8_t m_wbCqi
Wideband CQI.
std::vector< uint8_t > m_sbCqis
Subband CQI values.
uint8_t m_ri
the rank indicator, or simply the rank number
enum ns3::DlCqiInfo::DlCqiType WB
The type of the CQI.
uint16_t m_rnti
The RNTI.
A struct that contains info for the DL HARQ.
uint8_t m_numRetx
Num of Retx.
enum ns3::DlHarqInfo::HarqStatus NACK
HARQ status.
HarqStatus
Status of the DL Harq: ACKed or NACKed.
bool IsReceivedOk() const override
Information about the expected transport block at a certain point in the slot.
uint8_t m_ndi
New data indicator.
uint8_t m_rank
MIMO rank.
bool m_isDownlink
is Downlink?
uint16_t m_rnti
RNTI.
uint8_t m_harqProcessId
HARQ process ID (MAC)
uint8_t m_symStart
Sym start.
std::vector< int > m_rbBitmap
RB Bitmap.
uint8_t m_numSym
Num sym.
uint32_t m_tbSize
TBSize.
The GnbPhyPacketCountParameter struct.
Store information about HARQ.
uint8_t m_harqProcessId
ProcessId.
uint8_t m_bwpIndex
BWP identifier, uniquely identifies BWP within the UE.
uint16_t m_rnti
RNTI.
virtual bool IsReceivedOk() const =0
See section 4.3.14 macCEListElement.
The MacCeValue struct.
uint8_t raPreambleId
RA preamble ID, initialize with out of range values.
std::shared_ptr< DciInfoElementTdma > ulMsg3Dci
UL MSG3 DCI that will be sent through RAR message.
The structure used for the CQI feedback message that contains the optimum CQI, RI,...
Ptr< const ComplexMatrixArray > m_optPrecMat
Precoding matrix for each RB.
DlCqiInfo::DlCqiType m_cqiType
CQI type (WB or SB)
size_t m_wbPmi
Wideband precoding matrix index.
uint8_t m_rank
Rank of the channel matrix (supported number of MIMO layers)
uint8_t m_mcs
Modulation and coding scheme supported by current channel.
std::vector< size_t > m_sbPmis
Subband PMI values (i2, indices of W2 matrices)
uint8_t m_wbCqi
Wideband CQI.
size_t m_tbSize
Expected TB size when allocating all resources.
std::vector< uint8_t > m_sbCqis
Subband CQI values.
The RlcListElement struct.
The RlcPduInfo struct.
The RxPacketTraceParams struct.
The SlotAllocInfo struct.
SfnSf m_sfnSf
SfnSf of this allocation.
bool operator<(const SlotAllocInfo &rhs) const
operator < (less than)
AllocationType m_type
Allocations type.
std::vector< NrBuildRarListElement_s > m_buildRarList
build rar list that will be sent to UE
bool ContainsDlCtrlAllocation() const
void Merge(const SlotAllocInfo &other)
Merge the input parameter to this SlotAllocInfo.
uint32_t m_numSymAlloc
Number of allocated symbols.
bool ContainsUlCtrlAllocation() const
bool ContainsDataAllocation() const
Check if we have data allocations.
AllocationType
Enum which indicates the allocations that are inside the allocation info.
@ NONE
No allocations.
@ BOTH
DL and UL allocations.
@ UL
UL Allocations.
@ DL
DL Allocations.
bool ContainsUlMsg3Allocation() const
Check if we have UL MSG3 allocations.
std::deque< VarTtiAllocInfo > m_varTtiAllocInfo
queue of allocations
bool m_harqFeedbackSent
Indicate if the feedback has been sent for an entire TB.
double m_sinrMin
MIN SINR (only between the RB used to transmit the TB)
void UpdatePerceivedSinr(const SpectrumValue &perceivedSinr)
Update minimum and average SINR of the transport block based on perceived SINR.
ExpectedTb m_expected
Expected data from the PHY. Filled by AddExpectedTb.
double m_sinrAvg
AVG SINR (only for the RB used to transmit the TB)
bool m_isCorrupted
True if the ErrorModel indicates that the TB is corrupted.
Ptr< NrErrorModelOutput > m_outputOfEM
Output of the Error Model (depends on the EM type)
The UePhyPacketCountParameter struct.
The UlCqiInfo struct.
A struct that contains info for the UL HARQ.
uint8_t m_tpc
Transmit Power Control.
uint8_t m_numRetx
Num of Retx.
bool IsReceivedOk() const override
See section 4.3.4 logicalChannelConfigListElement.
enum ns3::nr::LogicalChannelConfigListElement_s::QosBearerType_e NotValid_QosBearerType
the QOS bearer type
uint64_t m_eRabMaximulBitrateUl
ERAB maximum bit rate UL.
uint64_t m_eRabMaximulBitrateDl
ERAB maximum bit rate DL.
uint64_t m_eRabGuaranteedBitrateUl
ERAB guaranteed bit rate UL.
uint8_t m_logicalChannelGroup
logical channel group
enum ns3::nr::LogicalChannelConfigListElement_s::Direction_e NotValid
the direction
uint64_t m_eRabGuaranteedBitrateDl
ERAB guaranteed bit rate DL.
uint8_t m_logicalChannelIdentity
logical channel identity
See section 4.3.14 macCEListElement.
enum ns3::nr::MacCeListElement_s::MacCeType_e NotValid
MAC CE type.
struct MacCeValue_u m_macCeValue
MAC CE value.
See section 4.3.15 macCEValue.
std::vector< uint8_t > m_bufferStatus
buffer status
See section 4.3.6 rachListElement.
uint16_t m_estimatedSize
estimated size
See section 4.3.3 vendorSpecificListElement.
Ptr< VendorSpecificValue > m_value
value
Base class for storing the values of vendor specific parameters.